View CY2CP1504ZXC_8556517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy2cp1504 1:4 lvcmos to lvpecl fanout buffer with selectable clock input cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-56313 rev. *f revised february 25, 2011 features select one of two low-voltage complementary metal oxide semiconductor (lvcmos) inputs to distribute to four low-voltage positive emitter-coupled logic (lvpecl) output pairs 30-ps maximum output-to-output skew 480-ps maximum propagation delay 0.15-ps maximum additive rms phase jitter at 156.25 mhz (12-khz to 20-mhz offset) up to 250 mhz operation synchronous clock enable function 20-pin thin shrunk small outline package (tssop) package 2.5-v or 3.3-v operating voltage [1] commercial and industrial operating temperature range functional description the cy2cp1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 lvcmos to lvpecl fanout buffer targeted to meet the requirements of high-speed clock distribution applications. the cy2cp1504 can select between two separate lvcmos input clo cks using the in_sel pin. the synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. the device has a fully differential internal architec ture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 250 mhz. note 1. input ac-coupling capacitors are required for voltage-translation applications. logic block diagram clk_en q0 q0# q1 q1# q2 q2# q3 q3# in0 in1 100k in_sel v dd v ss 100k vdd d q [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 2 of 13 contents pinouts .............................................................................. 3 absolute maximum ratings ............................................ 4 operating conditions....................................................... 4 dc electrical specifications ............................................ 5 ac electrical specifications ............................................ 6 ordering information........................................................ 9 ordering code definition............................................. 9 package dimension........................................................ 10 acronyms ........................................................................ 11 document conventions ................................................. 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design supp ort............. .......... 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 3 of 13 pinouts figure 1. pin diagram ? 20-pin tssop package 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 cy2cp1504 q0 q0# v dd q1 q1# q2 q2# v dd q3 q3# v ss clk_en in_sel in0 nc in1 nc nc nc v dd table 1. pin definitions pin no. pin name pin type description 1v ss power ground 2 clk_en input synchronous clock enable. lvcmos/low-voltage transistor-transistor logic (lvttl). when clk_en = low, q(0:3) outputs are held low and q(0:3)# outputs are held high 3 in_sel input input clock select pin. lvcmos/lvttl; when in_sel = low, input in0 is active when in_sel = high, input in1 is active 4 in0 input lvcmos input clock. active when in_sel = low 5,7,8,9 nc no connection 6 in1 input lvcmos input clock. active when in_sel = high 10,13,18 v dd power power supply 11,14,16,19 q(0:3)# output lvpec l complementary output clocks 12,15,17,20 q(0:3 ) output lvpecl output clocks [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 4 of 13 absolute maximum ratings parameter description condition min max unit v dd supply voltage nonfunctional ?0.5 4.6 v v in [2] input voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v v out [2] dc output or i/o voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v t s storage temperature nonfunctional ?55 150 c esd hbm electrostatic discharge (esd) protection (human body model) jedec std 22-a114-b 2000 ? v l u latch up meets or exceeds jedec spec jesd78b ic latchup test ul?94 flammability rating at 1/8 in v-0 msl moisture sensitivity level 3 operating conditions parameter description condition min max unit v dd supply voltage 2.5-v supply 2.375 2.625 v 3.3-v supply 3.135 3.465 v t a ambient operating temperature commercial 0 70 c industrial ?40 85 c t pu power ramp time power-up time for v dd to reach minimum specified voltage (power ramp must be monotonic) 0.05 500 ms note 2. the voltage on any i/o pin cannot exceed the power pin during power up. power supply sequencing is not required. [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 5 of 13 dc electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min max unit i dd operating supply current all l vpecl outputs float ing (internal i dd )? 61 ma v ih1 input high voltage, all inputs v dd = 3.3 v 2.0 v dd + 0.3 v v il1 input low voltage, all inputs v dd = 3.3 v ?0.3 0.8 v v ih2 input high voltage, all inputs v dd = 2.5 v 1.7 v dd + 0.3 v v il2 input low voltage, all inputs v dd = 2.5 v ?0.3 0.7 v i ih input high current, all inputs input = v dd [3] ? 150 a i il input low current, all inputs input = v ss [3] ?150 ? a v oh lvpecl output high voltage terminated with 50 to v dd ? 2.0 [4] v dd ? 1.20 v dd ? 0.70 v v ol lvpecl output low voltage terminated with 50 to v dd ? 2.0 [4] v dd ? 2.0 v dd ? 1.63 v r p internal pull-up/pull-down resistance clk_en has pull-up only in_sel has pull-down only 60 140 k c in input capacitance measured at 10 mhz; per pin ? 3 pf notes 3. positive current flows into the input pin, negative current flows out of the input pin. 4. refer to figure 2 on page 7. [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 6 of 13 ac electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85c (industrial)) parameter description condition min typ max unit f in input frequency dc ? 250 mhz f out output frequency f out = f in dc ? 250 mhz v pp lvpecl differential output voltage peak- to-peak, single-ended. terminated with 50 to v dd ? 2.0 [4] fout = dc to 150 mhz 600 ? ? mv fout = >150 mhz to 250 mhz 400 ? ? mv t pd [5] propagation delay input to output pair input rise/fall time < 1.5 ns (20% to 80%) ??480ps t odc [6] output duty cycle rail-to-rail input swing, 50% input dtcy measured at vdd/2 45?55% t sk1 [7] output-to-output skew any ou tput to any output, with same load conditions at dut ??30ps t sk1 d [7] device-to-device output skew any output to any output between two or more devices. devices must have the same input and have the same output load. ??150ps pn add additive rms phase noise 156.25-mhz input rise/fall time < 150 ps (20% to 80%) v id > 400 mv offset = 1 khz ? ? ?120 dbc/hz offset = 10 khz ? ? ?130 dbc/hz offset = 100 khz ? ? ?135 dbc/hz offset = 1 mhz ? ? ?150 dbc/hz offset = 10 mhz ? ? ?150 dbc/hz offset = 20 mhz ? ? ?150 dbc/hz t jit [8] additive rms phase jitter (random) 156.25 mhz sinewave, 12 khz to 20 mhz offset; input swing = 2.2v, v bias = v dd /2 ??0.15ps t r , t f [9] output rise/fall time 50% duty cycle at input, 20% to 80% of full swing (v ol to v oh ) input rise/fall time < 1.5 ns (20% to 80%) ??300ps t sod time from clock edge to outputs disabled synchronous clock enable (clk_en) switched low ??700ps t soe time from clock edge to outputs enabled synchronous clock enable (clk_en) switched high ??700ps notes 5. refer to figure 3 on page 7. 6. refer to figure 4 on page 7. 7. refer to figure 5 on page 7. 8. refer to figure 6 on page 8. 9. refer to figure 7 on page 8. [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 7 of 13 figure 2. output differential voltage figure 3. input to any output pair propagation delay figure 4. output duty cycle figure 5. output-to-outpu t and device-t o-device skew q v oh v ol q# v pp in t pd q x q x # t pw t odc = t pw t period t period q x # q x q x # q x q y # q y q z # q z t sk1 t sk1 d device 1 device 2 [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 8 of 13 figure 6. rms phase jitter figure 7. output rise/fall time figure 8. synchronous clock enable timing phase noise phase noise mark offset frequency f1 f2 a rea under the masked phase noise plot noise powe r rms jitter [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 9 of 13 ordering information ordering code definition part number type production flow pb-free CY2CP1504ZXC 20-pin tssop commercial, 0 c to 70 c CY2CP1504ZXCt 20-pin tssop tape and reel commercial, 0 c to 70 c cy2cp1504zxi 20-pin tssop industrial, ?40 c to 85 c cy2cp1504zxit 20-pin tssop tape and reel industrial, ?40 c to 85 c cy base part number 2cp15 04 number of differential output pairs company id: cy = cypress zx pb-free tssop package temperature range c = commercial i = industrial c/i t tape and reel [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 10 of 13 package dimension figure 9. 20-pin thin shrunk small outline package (4.40-mm body) zz20 51-85118 *c [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 11 of 13 acronyms document conventions table 2. acronyms used in this document acronym description esd electrostatic discharge hbm human body model jedec joint electron devices engineering council lvds low-voltage differential signal lvcmos low-voltage complementary metal oxide semiconductor lvpecl low-voltage positive emitter-coupled logic lvttl low-voltage transistor-transistor logic oe output enable rms root mean square tssop thin shrunk small outline package table 3. units of measure symbol unit of measure c degree celsius dbc decibels relati ve to the carrier ghz giga hertz hz hertz k kilo ohm a microamperes f micro farad s microsecond ma milliamperes ms millisecond mv millivolt mhz megahertz ns nanosecond ohm pf pico farad ps pico second vvolts wwatts [+] feedback
cy2cp1504 document number: 001-56313 rev. *f page 12 of 13 document history page document title: cy2cp1504 1:4 lvcmos to lvpec l fanout buffer with se lectable clock input document number: 001-56313 revision ecn orig. of change submission date description of change ** 2782891 cxq 10/09/09 new datasheet *a 2838916 cxq 05/01/2010 changed status from ?advance? to ?preliminary?. changed from 0.34 ps to 0.25 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table on page 5. added t pu spec to the operating conditions table on page 3. changed max i dd spec in the dc electrical specs table on page 4 from 60 ma to 61 ma. changed v oh in the dc electrical specs table on page 4: minimum from v dd - 1.15v to v dd - 1.20v; maximum from v dd - 0.75v to v dd - 0.70v. removed v od spec from the dc electrical specs table on page 4. added r p spec in the dc electrical specs table on page 4. min = 60 k , max = 140 k . added a measurement definition for c in in the dc electrical specs table on page 4. added v pp spec to the ac electrical specs table on page 5. v pp min = 600 mv for dc - 150 mhz and min = 400 mv for 150 mhz to 250 mhz. changed letter case and some names of all the timing parameters in the ac electrical specs table on page 5 to be consis tent with eros. lowered all additive phase noise mask specs by 3 db in the ac electrical specs table on page 5. added condition to t r and t f specs in the ac electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). changed letter case and some names of all the timing parameters in figures 2, 3, 4, 5 and 7, to be consistent with eros. *b 3011766 cxq 08/20/2010 changed from 0.25 ps to 0.15 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table on page 6. added note 2 to describe i ih and i il specs. removed reference to data distribution from ?functional description?. updated phase noise specs for 1 k/10 k/100 k/1 m/10 m/20 mhz offset to -120/-130/-135/-150/- 150/-150dbc/hz, respectively, in the ac electrical specs table. updated package diagram. added acronyms and ordering code definition. *c 3017258 cxq 08/27/2010 corrected outp ut rise/fall time diagram. *d 3100234 cxq 11/18/2010 changed v in and v out specs from 4.0v to ?lesser of 4.0 or v dd + 0.4? removed 200ma min lu spec, replaced wi th ?meets or exceeds jedec spec jesd78b ic latchup test? changed c in condition to ?measured at 10 mhz?. removed t r and t f input specs from ac specs table. changed t odc from 48/52% to 45/55%, changed condition to ?rail-to-rail input swing, 50% input duty cycl e measured at vdd/2?. changed phase jitter condition to ?156.25 mhz sinewave, 12 khz to 20 mhz offset; input swing = 2.2v, v bias = v dd /2 ? removed t s and t h specs from ac specs table. *e 3137726 cxq 01/13/2011 removed ?preliminary? status heading. removed resistors from in0/in1 in logic block diagram . added figure 8 to describe t soe and t sod . *f 3182321 cxq 02/25/11 post to external web. [+] feedback
document number: 001-56313 rev. *f revised february 25, 2011 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2cp1504 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY2CP1504ZXC

	To Download CY2CP1504ZXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .